1. Field of the Invention
The present invention generally relates to design supporting apparatuses being applicable to an analysis system or a design system and easily conducting a test, and more particularly to a design supporting apparatus capable of confirming a description of which a fault in a hardware functional description is difficult to be detected which is independent of an architecture when a large-scale integrated (LSI) circuit is tested by a function of a logic built-in self-test.
2. Description of the Related Art
For example, a conventional technology of a built-in self-test method (hereinafter, called logic BIST) of a scan-base using a random number for test data is disclosed in a Japanese Laid-open Patent Application No. 5-241882 and a Japanese Patent No. 2711492. Moreover, for example, a checking method for a functional description of a register transfer level is disclosed in Japanese Laid-open Patent Applications No. 11-85828, No. 2000-215225, and No 6-259496.
First, the Japanese Laid-open Patent Application No. 5-241882 describes advantages and disadvantages of a BIST circuit design having the function of the built-in self-test in an architecture. As the advantages, since a manufacturer is not required to cover time and cost necessary to embed a special test device in order to check a function and an operation of a circuit under test, test efficiency is improved. In addition, as the disadvantages, since it is required to assign a physical area within an IC (Integrated Circuit), an area for regular functional components is required to be smaller.
A circuit in the Japanese Laid-open Patent Application No. 5-241882 functions as a built-in self-test circuit (BIST) to test an operation of a circuit under test by generating a test vector and accumulating signals being output from the circuit under test in response to a test vector. A linear feedback shift register (LFSR) includes a first input being coupled to receive a signal output from the circuit under test, and an output to send a test vector to the circuit under test.
Next, the Japanese Patent No. 2711492 describes a distributed built-in self-test circuit for conducting a built-in self-test of a chip in a diagnostic test of an LSI design and a quality test at an LSI production, and more particularly to a pattern compressing device for the built-in self-test. That is, for the built-in self-test with respect to the LSI, it is required to arrange a pattern compressor for each of various functional blocks. Accordingly, because hardware of the built-in self-test is additionally arranged, a chip area is increased and a yield of the LSI is degraded. Therefore, an amount of hardware is required to be reduced as much as possible. As a spatial compressor built-in each functional block, various compressors having different configurations such as a compressor using a multiple input linear feedback shift register, a compressor using an exclusive OR, and a like are combined in sequence based on a smaller amount of hardware.
For example, the technologies described in the Japanese Laid-open Patent Applications No. 11-85828 and No. 6-259496 are related to a supporting apparatus to improve a test quality by a test bench that is created by a user, which warns a state coverage and an inactive state of a sequential circuit from a simulation result using the test bench created by the user.
Moreover, the Japanese Laid-open Patent Application No. 2000-215225 discloses a technology to examine data propagation from an input to an output based on a simulation result by a test bench created by a user, and to verify a test simplification.
Since test data are pseudo-random numbers in the logic BIST, there are cases in which a sufficient fault detection ratio cannot be obtained. In particular, a comparison operator including multiple bits is a circuit (random resistant) in which a fault detection using a pseudo-random number is not easily conducted. Regarding a circuit having an encoder and a conditional branch process being nested, if test data are pseudo-random numbers, a bias occurs after a conditional branch. As a result, there are circuits which remain without being tested.
Conventionally, in response to these problems, a technology is disclosed in U.S. Pat. No. 6,070,261 to insert a test circuit at a place where a controllability and an observability in a net list of gate levels are not good.
However, in this technology, because of the test circuit being inserted, a circuit function, especially, speed is degraded. In addition, in a case of a large-scale circuit, an execution time becomes longer in an analysis tool for the controllability and the observability.
In order to solve the above-described problems, for example, a description being difficult to detect a fault by the logic BIST is extracted at a register transfer level (hereinafter, called RTL), and a test circuit description is additionally described to the description being extracted. A net list of the gate level, in which a countermeasure is taken for the above-described problems, can be obtained.
However, it is required to know a description corresponding to a random resistance in the RTL beforehand.
Furthermore, in other than the test, an equivalence checking tool is not used for a multiplier having more than 32 bits in an equivalence checking process. Regarding the logic synthesis, if the multiplier is a large-scale circuit, the execution time becomes longer. In response to this problem, it is required to divide the description. In this case, it is needed to know where a problem is in the RTL beforehand.